Currently, with respect to a prospective pilot study, what is most concerned about is whether a CMOS device still can be based on a silicon semiconductor substrate as it was after the technology generation of 11 nm to 16 nm. One research focus is to develop a new material system with higher carrier mobility and a new technical means to further extend the Moore Law and Beyond Si-CMOS and promote the development of the integrated circuit technology.
The graphene material receives an extensive attention because of its excellent physical properties, such as high carrier mobility, high electrical conductivity, and high thermal conductivity, etc., and is a kind of carbon-based material which people feel very optimistic about. Although the graphene material shows many excellent physical properties, its application in a CMOS device as a channel material with high carrier mobility is confronted with many challenges. Currently, some studies show that the on-off ratio of a graphene device may be increased to some extent by increasing the band gap of the graphene, but at the same time at the cost of the carrier mobility of the graphene or the speed of the device.
Therefore, it is desirable to propose a graphene device structure and a method for manufacturing the same which is capable of increasing the on-off ratio of a graphene device without increasing the band gap of the graphene material, thereby not affecting the speed of the device.